1. Field of the Invention
The invention generally relates to memory devices and, more particularly, to reducing current consumption during refresh operations.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices.
DRAM devices utilize memory cells (also referred to as storage nodes) consisting of one transistor and one capacitor. The cells are accessed by activating a wordline, switching on the transistor and coupling the capacitor to a bit line. The stored charge on the capacitor is then sensed by a sense amplifier to determine if a logical ‘1’ or ‘0’ bit of data is stored in the accessed cell. Due to leakage current, charge stored in the capacitors may be lost to the point that the corresponding data is no longer valid.
As a result, DRAM devices need refresh operations to maintain their stored data. Refresh operations are typically performed at regular time intervals by means of activating a word line, or a number of word lines, followed by a pre-charge of the same word line or wordlines. This operation is repeated for the next word line or set of word lines until the whole chip is refreshed. Modern DRAM devices determine the word-line address for each refresh operation internally. Each refresh operation is either initiated externally, by means of an external command (e.g., a CAS before RAS or “CBR” refresh command) or internally when the device is in a “self refresh mode” or similar standby-like mode.
To optimize access to storage cells (e.g., to speed access, simplify signal routing, and/or facilitate layout), wordlines are sometimes grouped and controlled by master wordlines. FIG. 1 illustrates a conventional DRAM master wordline arrangement 100. During refresh operations, local wordlines or “wordline segments” 112, are activated by (a) activating the controlling master wordline 110 for the group and (b) asserting a signal on a control line 113 for a corresponding word line segment driver 114 for a particular wordline segment 112 while the master wordline 110 is activated. As illustrated in the refresh timing diagram of FIG. 2, in conventional DRAM devices, the master wordline is activated (204) before, and pre-charged (202) after, activating each wordline segment.
For special-purpose low power DRAM devices, such as those utilized in cellular telephones and personal digital assistants (PDAs), it is important to minimize current consumption, typically to increase battery life. As these devices often spend a large majority of their life in standby modes, requiring refresh to maintain their data (e.g., digital pictures, files, etc.), current consumption during refresh is particularly important. Unfortunately, each cycle of pre-charging and activating the master wordline during refresh operations of conventional DRAM devices results in additional current consumption.
Accordingly, it would be desirable to reduce the amount of current consumption caused by pre-charging and activating the master wordlines during refresh operations.